Signal Scrambling

When transmitting a signal, long sequence of same bit like $1111111\dots$ or $00000\dots$ make one steady voltage which can cause issues. Clock sync can be failed with no transitions to detect.

So a filling sequence is used to avoid these sequences by replacing them with a known pattern.

• Must produce enough transitions to sync
• Must be recognized by receiver and replace with original
• Same length as original

Advantages

• No dc component
• No long sequences of zero level line signal
• No reduction in data rate
• Error detection capability

B8ZS scheme

Bipolar with 8 zeros Substitution

This improves Encoding & Modulation#AMI Scheme

• eliminate the clock sync issue for large sequence of 0s (8 $0$s or more)
• do not introduce a DC component

This does it by purposefully introducing two AMI violation. (Which is two adjacent same bits Must have alternating polarities)

The first three 0s (aka octet) act as a detection signal. The last pulse before those (one in the left most) determine the violation polarity. Positive Pulse $\to {000+\underbrace{-0-}+}$ Negative Pulse $\to {000-\underbrace{+0+}-}$ This is for the first violations to happen with last pulse.

Two such violations are unlikely to occur in natural cases. Receiver detect it and mark them all zero.