Instructions Set Architecture
Overview
ISA is a Interface defined by some reputable body. Chip Manufacturers provide a Instructions Decoder that respect that instruction set. So same instructions can be executed in different Processors made by different parties.
The underlying way of performing those instructions are entirely up-to the manufacturer. They can make it as performant or efficient as they want. They just need to respect the Instruction.
For example, look at Apple and Qualcomm. Both use the ARM ISA . But underneath:
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Apple might decide to build massive "brain power" lanes (execution units) so it can process a ton of data at once, sacrificing a bit of physical space.
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Qualcomm might decide to optimize for thermal efficiency, building smaller lanes that don't get as hot in a smartphone.
Types of ISAs
There are mainly 2 types of ISAs.
- CISC ISA (Complex Instruction Set Computer)
- RISC ISA (Reduced Instruction Set Computer)
Comparison
| Feature | RISC | CISC |
|---|---|---|
| Core Philosophy | Minimal set of instructions | Powerful, multi-step instructions to do more per line of code and save memory. |
| Instruction Size | Fixed length (e.g., exactly 32 bits), making them very easy and fast to decode. | Variable length, meaning the CPU has to spend extra effort decoding. |
| Execution Speed | Almost every instruction = one clock cycle. | Complex instruction can take multiple clock cycles. |
| Memory Usage | Use 30-40% more memory for Program. Cache usage is highly optimized. | Minimal. But Complex to manage caches |
| Examples | ARM (found in iPhones, Androids, Nintendo Switch, Apple Silicon M-series) and [[RISC-V Architecture]]. | x86 (Intel and AMD processors found in most traditional PCs and servers). |
CISC Instruction
MULT A, BMeaning: Go to memory address A, go to memory address B, multiply them together, and overwrite the result back into memory address A.
Steps:
- Pause the CPU to fetch data from RAM address A.
- Fetch data from RAM address B.
- Send both to the execution unit to multiply them.
- Write the result back to RAM address A.
Single Instruction does so much work -> More clock cycles per instruction
RISC Instruction
LOAD R1, A ; Copy the data from RAM address A into CPU Register 1
LOAD R2, B ; Copy the data from RAM address B into CPU Register 2
MUL R3, R1, R2 ; Multiply Register 1 and Register 2, put the result in Register 3
STORE A, R3 ; Copy the result from Register 3 back into RAM address Avery small multiple instructions for the same process.
If RISC has 4 instructions to do CISC did in 1 instruction, what the heck is reduced??
What Reduced in RISC means
- The work single instruction has to do is reduced.
- The number of instructions defined is reduced.
The amount of instructions in a program will be larger. its not reduced. What is getting reduced is amount of work each instruction does.
Think of it as CISC has 5 MUL instructions for different multiply stuff.
IMUL AX, BX(Multiply two registers)IMUL AX, [1234](Multiply a register by a value sitting in a specific RAM address)IMUL AX, BX, 10(Multiply a register by a constant number, put it in another register)
RISC has only 1 simple multiply instruction
MUL R1, R2, R3(Multiply Register 2 by Register 3, put the result in Register 1)