Semester 3Computer Architecture
Memory Hierarchy
This is all about optimizing the cost while getting the best performance of memory.
locality
- temporal
- spacial
power wall problem dark silicon
types of cache misses compulsory capacity
conflict - direct mapping cache using modulo cache 4 units n % 4 = block number so mem blocks 2 and 10 will conflict
cache invalidation LRU policy
cache organization form of cache entry
- valid, dirty bit
- tag
- data
how the correct data is returned from cache just from the main memory address only the underlying table like structure is abstracted to outside cache uses indexing and tagging and offsets to pick up a word from the block of memory stored in there