RISC-V 5 Stage Pipeline

Confusion to solve

In RISC ISA, a single specific instruction might take 5 clock cycles to finish. But we usually say the RISC ISA support 1 instruction per cycle. What?

This is where the pipeline architecture comes in handy. RISC-V uses a 5 Stage Pipeline, that works continuously. So the processor does work in all five stages simultaneously. So even though, one specific instruction take 5 cycles to finish, the process finish 1 instruction per cycle.

Throughput vs Latency

Latency - How much time it takes for one instruction to be done Throughput - How much instructions getting done in some interval unit of time.

So One instruction might take 5 cycles, but in 5 cycles, 5 instructions will be finished.

This is why the five stages act as a waterfall, unlike a discrete blocks of work. Each stage does work at the same time.

The FIVE stages

1. IF – Instruction Fetch

• The Job: Get the instruction blueprint.
• What happens: The CPU looks at the Program Counter (PC) (the register that tracks what line of code you are on), goes to the code memory, sucks out the 32-bit instruction, and increments the PC to point to the next line.

2. ID – Instruction Decode / Register Read

• The Job: Figure out what we are doing and grab the tools.
• What happens: The hardware reads the opcode, funct3, and funct7 bits to see what type of instruction this is. At the exact same time, it instantly goes to the Register File to pull out the numbers stored in your source registers (rs1 and rs2).

3. EX – Execute / Address Calculation

• The Job: Do the physical math.
• What happens: This is where the ALU (the core calculator) turns on.
  • If it's an ADD instruction, it adds the two numbers together.
  • If it's a LW (Load Word) instruction, it calculates the RAM address by adding rs1 + immediate.

4. MEM – Memory Access

• The Job: Talk to the RAM (if necessary).
• What happens: * If the instruction is a standard math operation like ADD or ADDI, this stage does absolutely nothing—the instruction just steps through it to keep the line moving.
  • If it's a LW (Load) or SW (Store), this is the exact moment the CPU opens the gate to the external system RAM to either read data out or write data in.

5. WB – Writeback

• The Job: Record the final result.
• What happens: The instruction takes its final answer (either the math result from the EX stage or the RAM data from the MEM stage) and physically writes it back into the destination register (rd). The instruction is now officially complete.